TAS5709
SLOS599–NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
AC Characteristics (BTL)
PVDD_X = 18 V, BTL AD mode, FS = 48 KHz, RL = 8 Ω, ROCP = 22 KΩ, CBST = 33 nF, audio frequency = 1 kHz, AES17 filter,
fPWM = 384 kHz, TA = 25°C (unless otherwise noted). All performance is in accordance with recommended operating
conditions, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
20.6
19.5
MAX UNIT
PVDD = 18 V,10% THD, 1-kHz input signal
PVDD = 18 V, 7% THD, 1-kHz input signal
PVDD = 12 V, 10% THD, 1-kHz input
signal
9.4
PO
Power output per channel
W
PVDD = 12 V, 7% THD, 1-kHz input signal
PVDD = 8 V, 10% THD, 1-kHz input signal
PVDD = 8 V, 7% THD, 1-kHz input signal
PVDD= 18 V; PO = 1 W
8.9
4.1
3.8
0.06%
0.13%
0.2%
56
THD+N
Vn
Total harmonic distortion + noise
PVDD= 12 V; PO = 1 W
PVDD= 8 V; PO = 1 W
Output integrated noise (rms)
Crosstalk
A-weighted
µV
dB
dB
PO = 0.25 W, f = 1kHz (BD Mode)
PO = 0.25 W, f = 1kHz (AD Mode)
–82
-69
A-weighted, f = 1 kHz, maximum power at
THD < 1%
(1)
SNR
Signal-to-noise ratio
106
dB
(1) SNR is calculated relative to 0-dBFS input level.
SERIAL AUDIO PORTS SLAVE MODE
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
12.288
UNIT
fSCLKIN
tsu1
Frequency, SCLK 32 × fS, 48 × fS, 64 × fS
Setup time, LRCLK to SCLK rising edge
Hold time, LRCLK from SCLK rising edge
Setup time, SDIN to SCLK rising edge
Hold time, SDIN from SCLK rising edge
LRCLK frequency
CL = 30 pF
1.024
10
MHz
ns
th1
10
ns
tsu2
10
ns
th2
10
ns
8
48
50%
50%
48
60%
60%
kHz
SCLK duty cycle
40%
40%
LRCLK duty cycle
SCLK
edges
SCLK rising edges between LRCLK rising edges
LRCLK clock edge with respect to the falling edge of SCLK
Rise/fall time for SCLK/LRCLK
32
64
1/4
8
t(edge)
SCLK
period
–1/4
tr /
ns
tf(SCLK/LRCLK)
10
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