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TAS5707 参数 Datasheet PDF下载

TAS5707图片预览
型号: TAS5707
PDF下载: 下载PDF文件 查看货源
内容描述: 具有EQ和DRC的20W立体声数字音频功率放大器 [20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC]
分类和应用: 放大器功率放大器
文件页数/大小: 55 页 / 1219 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TAS5707  
www.ti.com ........................................................................................................................................................................................... SLOS556NOVEMBER 2008  
OSCILLATOR TRIM REGISTER (0x1B)  
The TAS5707 PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This  
reduces system cost because an external reference is not required. Currently, TI recommends a reference  
resistor value of 18.2 k(1%). This should be connected between OSC_RES and DVSSO.  
Writing 0X00 to reg 0X1B enables the trim that was programmed at the factory.  
Note that trim must always be run following reset of the device.  
Table 16. Oscillator Trim Register (0x1B)  
D7  
1
D6  
D5 D4 D3  
D2  
D1  
D0  
FUNCTION  
(1)  
0
0
0
Reserved  
(1)  
0
Oscillator trim not done (read-only)  
1
Oscillator trim done (read only)  
(1)  
0
Reserved  
0
Select factory trim (Write a 0 to select factory trim; default is 1.)  
(1)  
1
Factory trim disabled  
(1)  
0
Reserved  
(1) Default values are in bold.  
BKND_ERR REGISTER (0x1C)  
When a back-end error signal is received from the internal power stage, the power stage is reset stopping all  
PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 17 before attempting  
to re-start the power stage.  
Table 17. BKND_ERR Register (0x1C)(1)  
D7 D6 D5 D4 D3  
D2  
0
D1  
0
D0  
X
0
FUNCTION  
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Reserved  
(2)  
0
1
Set back-end reset period to 299 ms  
Set back-end reset period to 449 ms  
Set back-end reset period to 598 ms  
Set back-end reset period to 748 ms  
Set back-end reset period to 898 ms  
Set back-end reset period to 1047 ms  
Set back-end reset period to 1197 ms  
Set back-end reset period to 1346 ms  
Set back-end reset period to 1496 ms  
Set back-end reset period to 1496 ms  
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
X
X
1
X
(1) This register can be written only with a "non-Reserved" value. Also this register can be written once after the reset.  
(2) Default values are in bold.  
Copyright © 2008, Texas Instruments Incorporated  
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Product Folder Link(s): TAS5707  
 
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