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TAS5707 参数 Datasheet PDF下载

TAS5707图片预览
型号: TAS5707
PDF下载: 下载PDF文件 查看货源
内容描述: 具有EQ和DRC的20W立体声数字音频功率放大器 [20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC]
分类和应用: 放大器功率放大器
文件页数/大小: 55 页 / 1219 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TAS5707  
www.ti.com ........................................................................................................................................................................................... SLOS556NOVEMBER 2008  
Normal Operation  
The following are the only events supported during normal operation:  
(a) Writes to master/channel volume registers  
(b) Writes to soft mute register  
(c) Enter and exit shutdown (sequence defined below)  
(d) Clock errors and rate changes  
Note: Events (c) and (d) are not supported for 240ms+1.3*Tstart after trim following AVDD/DVDD powerup  
ramp (where Tstart is specified by register 0x1A).  
Shutdown Sequence  
Enter:  
1. Ensure I2S clocks have been stable and valid for at least 50ms.  
2. Write 0x40 to register 0x05.  
3. Wait at least 1ms+1.3*Tstop (where Tstop is specified by register 0x1A).  
4. Once in shutdown, stable clocks are not required while device remains idle.  
5. If desired, reconfigure by ensuring that clocks have been stable and valid for at least 50ms before  
returning to step 4 of initialization sequence.  
Exit:  
1. Ensure I2S clocks have been stable and valid for at least 50ms.  
2. Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240ms  
after trim following AVDD/DVDD powerup ramp).  
3. Wait at least 1ms+1.3*Tstart (where Tstart is specified by register 0x1A).  
4. Proceed with normal operation.  
Powerdown Sequence  
Use the following sequence to powerdown the device and its supplies:  
1. If time permits, enter shutdown (sequence defined above); else, in case of sudden power loss,  
assert PDNZ=0 and wait at least 2ms.  
2. Assert RESETZ=0.  
3. Drive digital inputs low and ramp down PVDD supply as follows:  
Drive all digital inputs low after RESETZ has been low for at least 2us.  
Ramp down PVDD while ensuring that it remains above 8V until RESETZ has been low for at  
least 2us.  
4. Ramp down AVDD/DVDD while ensuring that it remains above 3V until PVDD is below 6V and  
that it is never more than 2.5V below the digital inputs.  
Copyright © 2008, Texas Instruments Incorporated  
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