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TAS5705PAP 参数 Datasheet PDF下载

TAS5705PAP图片预览
型号: TAS5705PAP
PDF下载: 下载PDF文件 查看货源
内容描述: 具有EQ和DRC的20W立体声数字音频功率放大器 [20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC]
分类和应用: 消费电路商用集成电路音频放大器视频放大器功率放大器
文件页数/大小: 71 页 / 1403 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TAS5705  
www.ti.com ...................................................................................................................................................................................................... SLOS549JUNE 2008  
By default, bits 2:0 have the value 000; that means the bank switch is disabled. In that state, any update to  
locations 0x29–0x3F go into the DAP. A write to register 0x50 with bits 2:0 being 001, 010, or 011 brings the  
system into the coefficient-bank-update state update bank1, update bank2, or update bank3, respectively. Any  
subsequent write to locations 0x29–0x3F updates the coefficient banks stored outside the DAP. After updating all  
the three banks, the system controller should issue a write to register 0x50 with bits 2:0 being 100; this changes  
the system state to automatic bank update. In automatic bank update, the TAS5705 automatically swaps banks  
based on the sample rate.  
In the headphone mode, speaker equalization and DRC are disabled, and they are restored on returning to the  
speaker mode.  
Command sequences for initialization can be summarized as follows:  
1. Enable factory trim for internal oscillator: Write to register 0x1B with a value 0x00.  
2. Update coefficients: Coefficients can be loaded into DAP RAM using the manual bank mode.  
OR  
Use automatic bank mode.  
a. Enable bank-1 mode: Write to register 0x50 with 0x01. Load the 32-kHz coefficients. TI ALE  
can generate coefficients.  
b. Enable bank-2 mode: Write to register 0x50 with 0x02. Load the 48-kHz coefficients.  
c. Enable bank-3 mode: Write to register 0x50 with 0x03. Load the other coefficients.  
d. Enable automatic bank switching by writing to register 0x50 with 0x04.  
3. Bring the system out of all-channel shutdown: Write 0 to bit 6 of register 0x05.  
4. Issue master volume: Write to register 0x07 with the volume value (0 db = 0x30).  
Interchannel Delay (ICD) Settings  
Table 6. Recommended ICD Settings  
Mode  
Description  
ICD1  
ICD2  
ICD3  
B(L–) = –24 = D(R–) = 18 =  
(0xA0) (0x48)  
ICD4  
ICD5  
SM(S–) = –3 = SP(S+) = 3 =  
(0xF4) (0x0C)  
ICD6  
BD  
2 BTL channels, internal A(L+) = –18  
power stage only, BD  
mode  
C(R+) = 24 =  
(0x60)  
(0xB8)  
AD  
2 internal BTL channels, A(L+) = 21 =  
C(R+) = 21  
(0x54)  
B(L–) = –21 = D(R–) = 21 =  
(0xAC) (0x54)  
SM(S–) = 0 = SP(S+) = 0 =  
(0x00) (0x00)  
1 external BTL channel  
using PBTL TAS5601,  
AD mode  
(0xAC)  
Copyright © 2008, Texas Instruments Incorporated  
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Product Folder Link(s): TAS5705  
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