TAS5705
SLOS549–JUNE 2008...................................................................................................................................................................................................... www.ti.com
Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data-bit positions.
2-Channel Left-Justified Stereo Input
32 Clks
32 Clks
LRCLK
SCLK
Right Channel
Left Channel
SCLK
MSB
LSB MSB
23 22
LSB
24-Bit Mode
23 22
9
5
1
8
4
0
5
1
4
0
1
9
5
1
8
4
0
5
1
4
0
1
0
0
20-Bit Mode
19 18
19 18
15 14
16-Bit Mode
15 14
T0034-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 31. Left-Justified 64-fS Format
28
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