TAS5705
www.ti.com ...................................................................................................................................................................................................... SLOS549–JUNE 2008
In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is
designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins
(BST_X), and power-stage supply pins (PVDD_X). The gate drive voltages (GVDD_AB and GVDD_CD) are
derived from the PVDD voltage. Separate, internal voltage regulators reduce and regulate the PVDD voltage to a
voltage appropriate for efficient gave drive operation. Special attention should be paid to placing all decoupling
capacitors as close to their associated pins as possible. In general, inductance between the power-supply pins
and decoupling capacitors must be avoided.
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 352 kHz to 384 kHz, it is recommended to use 33-nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even
during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the
remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin.
The TAS5705 is fully protected against erroneous power-stage turnon due to parasitic gate charging.
SYSTEM POWER-UP/POWER-DOWN SEQUENCE
Powering Up
The outputs of the H-bridges remain in a low-impedance state until the internal gate-drive supply voltage
(GVDD_XY) and external VREG voltages are above the undervoltage protection (UVP) voltage threshold (see
the DC Characteristics section of this data sheet). It is recommended to hold PVDD_X low until DVDD (3.3 V) is
powered up while powering up the device. This allows an internal circuit to charge the external bootstrap
capacitors by enabling a weak pulldown of the half-bridge output. The output impedance is approximately 3 kΩ.
This means that the TAS5705 should be held in reset for at least 100 µs to ensure that the bootstrap capacitors
are charged. This also assumes that the recommended 0.033-µF bootstrap capacitors are used. Changes to
bootstrap capacitor values change the bootstrap capacitor charge time. See Figure 7 and Figure 8.
Powering Down
Apply PDN (assert low). Wait for the power stage to shut down. Power down PVDD. Then power down DVDD.
Then de-assert PDN. See Figure 8 for recommended timing.
ERROR REPORTING
The FAULT pin is an active-low, open-drain output. Its function is for protection-mode signaling to a
system-control device.
Any fault resulting in device shutdown is signaled by the FAULT pin going low (see Table 1).
Table 1. FAULT Output States
FAULT
DESCRIPTION
0
1
Overcurrent (OC) or undervoltage (UVP) warning or overtemperature error (OTE)
Junction temperature lower than 150°C and no faults (normal operation)
Note that asserting RESET low forces the FAULT signal high, independent of faults being present.
To reduce external component count, an internal pullup resistor to 3.3 V is provided on the FAULT output. Level
compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see the Electrical
Characteristics section of this data sheet for further specifications).
Copyright © 2008, Texas Instruments Incorporated
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