TAS5701
www.ti.com ...................................................................................................................................................................................................... SLOS559–JUNE 2008
1/f
S
LRCK
SCLK
L-Channel
R-Channel
(= 32 f , 48 f or 64 f
)
S
S
S,
16-Bit Right-Justified, SCLK = 48 f or 64 f
S
S
DATA
2
1
0
15 14 13
2
2
1
0
15 14 13
2
2
1
0
0
MSB
MSB
LSB
LSB
16-Bit Right-Justified, SCLK = 32 f
S
DATA
2
1
0
15 14 13
MSB
1
0
15 14 13
MSB
1
LSB
LSB
18-Bit Right-Justified, SCLK = 48 f or 64 f
S
S
DATA
2
1
0
17 16 15
MSB
2
2
1
0
0
17 16 15
MSB
2
2
1
0
0
LSB
LSB
20-Bit Right-Justified, SCLK = 48 f or 64 f
S
S
2
1
0
19 18 17
MSB
1
19 18 17
MSB
1
DATA
LSB
LSB
24-Bit Right-Justified, SCLK = 48 f
S
DATA
2
1
0
23 22 21
2
2
1
0
0
23 22 21
MSB
2
2
1
0
0
LSB
LSB
MSB
24-Bit Right-Justified, SCLK = 64 f
S
DATA
2
1
0
23 22 21
MSB
1
23 22 21
MSB
1
LSB
LSB
Figure 20. Right-Justified Format
Format Control
The digital data input format is selected via three external terminals (FORMAT0, FORMAT1, and FORMAT2).
Table 1 lists the corresponding data format for SDIN1 and SDIN2. LRCLK and SCLK are shared clocks for
SDIN1 and SDIN2. Changes to the FORMATx terminals are latched in immediately on a rising edge of RESET.
Changes to the FORMATx terminals while RESET is high are not allowed.
Table 1. Format Control
SERIAL DIGITAL DATA
FORMAT2
FORMAT1
FORMAT0
FORMAT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16-Bit right-justifed
18-Bit right-justified
20-Bit right-justified
24-Bit right-justified
16-, 24-Bit I2S
16-, 24-Bit left-justified
Reserved. Setting is not allowed.
Reserved. Setting is not allowed.
Copyright © 2008, Texas Instruments Incorporated
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