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SCES212V – APRIL 1999 – REVISED FEBRUARY 2010
SINGLE 2-INPUT POSITIVE-NAND GATE
Check for Samples:
1
FEATURES
Available in the Texas Instruments NanoStar™
Package
Supports 5-V V
CC
Operation
Inputs Accept Voltages to 5.5 V
Max t
pd
of 3.8 ns at 3.3 V
Low Power Consumption, 10-mA Max I
CC
±24-mA Output Drive at 3.3 V
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
•
•
•
•
•
•
•
•
•
I
off
Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
DRL PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
A
B
GND
1
5
V
CC
A
B
1
2
3
5
V
CC
A
B
GND
1
2
3
5
V
CC
Y
GND
B
A
3 4
2
1 5
Y
V
CC
2
4
GND
4
4
Y
3
Y
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC1G00 performs the Boolean function Y = A
●
B or Y = A + B in positive logic.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
–40°C to 85°C
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
SOT (SOT-553) – DRL
(1)
(2)
(3)
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 4000
ORDERABLE PART NUMBER
SN74LVC1G00YZPR
SN74LVC1G00DBVR
SN74LVC1G00DBVT
SN74LVC1G00DCKR
SN74LVC1G00DCKT
SN74LVC1G00DRLR
CA_
TOP-SIDE MARKING
(3)
_ _ _ CA_
C00_
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at
Package drawings, thermal data, and symbolization are available at
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
●
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2010, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
