SINGLE 2-INPUT POSITIVE-AND GATE
SCES217T – APRIL 1999 – REVISED FEBRUARY 2007
www.ti.com
ORDERING INFORMATION
T
A
PACKAGE
(1)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
SON – DRY
–40°C to 85°C
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
SOT (SOT-553) – DRL
(1)
(2)
Reel of 3000
Reel of 5000
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 4000
ORDERABLE PART
NUMBER
SN74LVC1G08YZPR
SN74LVC1G08DRYR
SN74LVC1G08DBVR
SN74LVC1G08DBVT
SN74LVC1G08DCKR
SN74LVC1G08DCKT
SN74LVC1G08DRLR
CE_
TOP-SIDE MARKING
(2)
_ _ _CE_
CE _
C08_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK/DRL/DRY: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
•
= Pb-free).
FUNCTION TABLE
INPUTS
A
H
L
X
B
H
X
L
OUTPUT
Y
H
L
L
LOGIC DIAGRAM (POSITIVE LOGIC)
2
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