1G175
SINGLE D-TYPE FLIP-FLOP WITH ASYNCHRONOUS CLEAR
● Complementary Outputs (Q, Q)
● Buffered Clock and Direct Clear Inputs
● Asynchronous Clear Function
Logic Diagram
6
CLR
1
CLK
3
D
R
D
4
Q
C1
FUNCTION TABLE
INPUTS
OUTPUT
Q
CLR CLK
D
L
H
H
H
L
↑
↑
L
H
X
X
H
H or L
X
Q
O
L
ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
MAX or MIN
PARAMETER
UNIT
MAX
MAX
MAX
0.01
-32
32
0.01
-24
24
0.01
-8
0.01
-4
mA
mA
mA
I
CC
I
OH
I
OL
8
4
TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
PARAMETER
INPUT
OUTPUT
MAX or MIN
MIN
MIN
MIN
MIN
MIN
MIN
f
t
175
2.5
2.5
1.5
0.5
0.5
4
150
2.8
2.8
2
125
3
100
5.6
3.5
3
max
CLR
CLK
Data
Low
High or low
Pulse duration
w
3
2.5
0
Setup time, before CLK ↑
Hold time, data after CLK ↑
t
su
0.5
0.5
5.7
5.7
5.8
5.8
0
CLR inactive
0
0
t
t
t
t
t
h
7.1
7.1
7
13.4
13.4
12.9
12.9
PLH
PHL
PLH
PHL
CLK
Q
Q
MAX
MAX
4
4.1
4.1
CLR
7
UNIT f
: MHz other : ns
max
113
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
TI [ TEXAS INSTRUMENTS ]
