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3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS143R – MAY 1992 – REVISED NOVEMBER 2006
GRD OR ZRD PACKAGE
(TOP VIEW)
1
2
3
4
5
6
TERMINAL ASSIGNMENTS
(1)
(54-Ball GRD/ZRD Package)
1
A
1B1
1B3
1B5
1B7
2B1
2B3
2B5
2B7
2B8
B
C
D
E
F
G
H
J
2
NC
1B2
1B4
1B6
1B8
2B2
2B4
2B6
NC
3
1DIR
NC
V
CC
GND
GND
GND
V
CC
NC
2DIR
4
1OE
NC
V
CC
GND
GND
GND
V
CC
NC
2OE
5
NC
1A2
1A4
1A6
1A8
2A2
2A4
2A6
NC
6
1A1
1A3
1A5
1A7
2A1
2A3
2A5
2A7
2A8
A
B
C
D
E
F
G
H
J
(1)
NC – No internal connection
FUNCTION TABLE
(1)
(EACH 8-BIT SECTION)
CONTROL
INPUTS
OE
L
L
H
(1)
DIR
L
H
X
OUTPUT CIRCUITS
OPERATION
A PORT
Enabled
Hi-Z
Hi-Z
B PORT
Hi-Z
Enabled
Hi-Z
B data to A bus
A data to B bus
Isolation
Input circuits of the data I/Os always are active.
LOGIC DIAGRAM (POSITIVE LOGIC)
1DIR
1
2DIR
48
24
1OE
25
2OE
1A1
47
2A1
36
2
1B1
13
2B1
To Seven Other Channels
To Seven Other Channels
3
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