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SN74LVC1G08DBVR 参数 Datasheet PDF下载

SN74LVC1G08DBVR图片预览
型号: SN74LVC1G08DBVR
PDF下载: 下载PDF文件 查看货源
内容描述: 单路2输入正与门 [SINGLE 2-INPUT POSITIVE-AND GATE]
分类和应用: 栅极触发器逻辑集成电路光电二极管输入元件PC
文件页数/大小: 16 页 / 434 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SN74LVC1G08
SINGLE 2 INPUT POSITIVE AND GATE
SCES217S − APRIL 1999 − REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
S1
VLOAD
Open
GND
RL
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
VLOAD
GND
From Output
Under Test
CL
(see Note A)
RL
LOAD CIRCUIT
INPUTS
VCC
1.8 V
±
0.15 V
2.5 V
±
0.2 V
3.3 V
±
0.3 V
5 V
±
0.5 V
VI
VCC
VCC
3V
VCC
tr/tf
≤2
ns
≤2
ns
≤2.5
ns
≤2.5
ns
VM
VCC/2
VCC/2
1.5 V
VCC/2
VLOAD
2
×
VCC
2
×
VCC
6V
2
×
VCC
CL
15 pF
15 pF
15 pF
15 pF
RL
1 MΩ
1 MΩ
1 MΩ
1 MΩ
V
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
tw
VI
Input
VM
VM
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VI
Input
tPLH
Output
tPHL
VM
VM
VM
VM
0V
tPHL
VOH
VM
VOL
tPLH
VOH
Output
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
Output
Control
tPZL
VM
tPZH
VM
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
VM
0V
tPLZ
VLOAD/2
VOL + V
tPHZ
VOH − V
VOH
≈0
V
VOL
Data Input
tsu
VM
th
VI
VM
0V
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
5