SN74LVC1G04
SINGLE INVERTER GATE
www.ti.com
SCES214S–APRIL 1999–REVISED OCTOBER 2005
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(2)
NanoStar™ – WCSP (DSBGA)
0.17-mm Small Bump – YEA
SN74LVC1G04YEAR
SN74LVC1G04YZAR
SN74LVC1G04YEPR
SN74LVC1G04YZPR
NanoFree™ – WCSP (DSBGA)
0.17-mm Small Bump – YZA
(Pb-free)
_ _ _CC_
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
Reel of 3000
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
–40°C to 85°C
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YZV
(Pb-free)
SN74LVC1G04YZVR
PREVIEW
C04_
Reel of 3000 SN74LVC1G04DBVR
Reel of 250 SN74LVC1G04DBVT
Reel of 3000 SN74LVC1G04DCKR
Reel of 250 SN74LVC1G04DCKT
Reel of 4000 SN74LVC1G04DRLR
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
CC_
SOT (SOT-553) – DRL
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP/YZV: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and
one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUT
A
OUTPUT
Y
H
L
L
H
LOGIC DIAGRAM (POSITIVE LOGIC)
(DBV, DCK, DRL, YEA, YEP, YZA, AND YZP PACKAGE)
2
4
A
Y
LOGIC DIAGRAM (POSITIVE LOGIC)
(YZV PACKAGE)
1
3
A
Y
2
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