SN74LVC1G04
SINGLE INVERTER GATE
SCES214S – APRIL 1999 – REVISED OCTOBER 2005
www.ti.com
ORDERING INFORMATION
T
A
PACKAGE
(1)
NanoStar™ – WCSP (DSBGA)
0.17-mm Small Bump – YEA
NanoFree™ – WCSP (DSBGA)
0.17-mm Small Bump – YZA
(Pb-free)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YZV
(Pb-free)
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
SOT (SOT-553) – DRL
(1)
(2)
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 4000
Reel of 3000
ORDERABLE PART NUMBER
SN74LVC1G04YEAR
SN74LVC1G04YZAR
_ _ _CC_
SN74LVC1G04YEPR
SN74LVC1G04YZPR
TOP-SIDE MARKING
(2)
–40°C to 85°C
SN74LVC1G04YZVR
SN74LVC1G04DBVR
SN74LVC1G04DBVT
SN74LVC1G04DCKR
SN74LVC1G04DCKT
SN74LVC1G04DRLR
PREVIEW
C04_
CC_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP/YZV: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and
one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
•
= Pb-free).
FUNCTION TABLE
INPUT
A
H
L
OUTPUT
Y
L
H
LOGIC DIAGRAM (POSITIVE LOGIC)
(DBV, DCK, DRL, YEA, YEP, YZA, AND YZP PACKAGE)
A
2
4
Y
LOGIC DIAGRAM (POSITIVE LOGIC)
(YZV PACKAGE)
A
1
3
Y
2
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