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ꢊ ꢋꢌꢍꢎ ꢋꢏꢐ ꢑ ꢒꢋꢀ ꢒꢋꢓ ꢓ ꢑꢎ ꢔ ꢌꢕꢑ
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ꢖ ꢗꢕ ꢄ ꢘ ꢙꢀꢕꢌꢕ ꢑ ꢚ ꢋꢕ ꢏ ꢋꢕ
SCLS104D − MARCH 1984 − REVISED AUGUST 2003
D
D
Wide Operating Voltage Range of 2 V to 6 V
D
D
D
Typical t = 11 ns
pd
6-mA Output Drive at 5 V
High-Current 3-State Outputs Interface
Directly With System Bus or Can Drive Up
To 15 LSTTL Loads
Low Input Current of 1 µA Max
D
Low Power Consumption, 80-µA Max I
CC
SN54HC125 . . . FK PACKAGE
(TOP VIEW)
SN54HC125 . . . J OR W PACKAGE
SN74HC125 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1OE
1A
V
CC
13 4OE
1
2
3
4
5
6
7
14
3
2
1
20 19
18
4A
NC
4Y
1Y
NC
4
5
6
7
8
12
11
10
9
1Y
4A
17
16
2OE
2A
4Y
2OE
NC
3OE
3A
15 NC
14
9 10 11 12 13
2Y
3OE
2A
8
GND
3Y
NC − No internal connection
description/ordering information
These quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled
when the associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube of 25
Tube of 50
Reel of 2500
Reel of 250
Reel of 2000
Reel of 2000
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
SN74HC125N
SN74HC125N
SN74HC125D
SN74HC125DR
SN74HC125DT
SN74HC125NSR
SN74HC125DBR
SN74HC125PWR
SN74HC125PWT
SNJ54HC125J
SNJ54HC125W
SNJ54HC125FK
HC125
−40°C to 85°C
SOP − NS
HC125
HC125
SSOP − DB
TSSOP − PW
HC125
CDIP − J
CFP − W
LCCC − FK
SNJ54HC125J
SNJ54HC125W
SNJ54HC125FK
−55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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