SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS115D – DECEMBER 1982 – REVISED AUGUST 2003
FUNCTION TABLE
INPUTS
CLR
L
H
H
H
H
CLK
X
L
↑
↑
↑
A
X
X
H
L
X
B
X
X
H
X
L
QA
L
QA0
H
L
L
OUTPUTS
QB . . . QH
L
QB0
QAn
QAn
QAn
L
QH0
QGn
QGn
QGn
QA0, QB0, QH0 = the level of QA, QB, or QH, respectively,
before the indicated steady-state input conditions were
established
QAn, QGn = the level of QA or QG before the most recent
↑
transition of CLK: indicates a 1-bit shift
logic diagram (positive logic)
CLK
8
A
B
CLR
1
2
9
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
3
QA
4
QB
5
QC
6
QD
10
QE
11
QF
12
QG
13
QH
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
2
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