SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS115D – DECEMBER 1982 – REVISED AUGUST 2003
FUNCTION TABLE
INPUTS
OUTPUTS
. . . Q
CLR
L
CLK
X
A
X
X
H
L
B
X
X
H
X
L
Q
Q
B
A
H
L
L
L
H
L
Q
Q
Q
H0
Q
Gn
Q
Gn
Q
Gn
A0
B0
An
An
An
H
↑
H
L
L
Q
Q
Q
H
↑
H
↑
X
Q
, Q , Q = the level of Q , Q , or Q , respectively,
A0 B0 H0 A B H
before the indicated steady-state input conditions were
established
Q
, Q = the level of Q or Q before the most recent
An Gn A G
↑ transition of CLK: indicates a 1-bit shift
logic diagram (positive logic)
8
CLK
1
2
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
A
B
R
R
R
R
R
R
R
R
9
CLR
3
4
5
6
10
11
12
13
Q
Q
Q
Q
Q
Q
Q
Q
H
A
B
C
D
E
F
G
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
2
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