SN54F32, SN74F32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDFS044B – MARCH 1987 – REVISED MAY 1999
PARAMETER MEASUREMENT INFORMATION
500
Ω
S1
7V
Open
From Output
Under Test
CL
(see Note A)
Test
Point
500
Ω
From Output
Under Test
CL
(see Note A)
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Collector
S1
Open
7V
Open
7V
500
Ω
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
3V
Timing Input
tw
3V
tsu
Data Input
0V
1.5 V
1.5 V
0V
th
3V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
3V
1.5 V
tPZL
1.5 V
tPZH
VOH
1.5 V
1.5 V
VOL
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
1.5 V
0V
tPLZ
≈
3.5 V
VOL + 0.3 V
tPHZ
VOH – 0.3 V
VOH
≈
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
VOL
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
Input
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
1.5 V
1.5 V
0V
tPHL
1.5 V
1.5 V
VOH
VOL
tPLH
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr
≤
2.5 ns, tf
≤
2.5 ns,
duty cycle = 50%.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
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DALLAS, TEXAS 75265
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