SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
typical clear, preset, count, and inhibit sequences
The following sequence is illustrated below:
1. Clear outputs to zero (SN74ALS867A and
′AS867
are asynchronous;
SN74ALS869 and
′AS869
are synchronous.)
2. Preset to binary 252
3. Count up to 253, 254, 255, 0, 1, and 2
4. Count down to 1, 0, 255, 254, 253, and 252
5. Inhibit
S0
S1
A
B
C
Data
Inputs
D
E
F
G
H
CLK
ENP
ENT
QA
QB
QC
QD
Outputs
QE
QF
QG
QH
RCO
Sync
252 253 254 255 0 1
Clear
Count Up
Async Preset
Clear
† ENT and ENP both must be low for counting to occur.
2
1
0
255 254 253 252
Count Down
Inhibit†
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
7
TI [ TEXAS INSTRUMENTS ]
