SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004
SN5404, SN54LS04, SN54S04,
SN7404, SN74LS04, SN74S04
HEX INVERTERS
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
VCC
Test
Point
VCC
VCC
RL
From Output
Under Test
CL
(see Note A)
RL
(see Note B)
From Output
Under Test
CL
(see Note A)
Test
Point
S2
Test
Point
RL
S1
(see Note B)
5 kΩ
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
High-Level
Pulse
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
Timing
Input
tsu
1.3 V
Data
Input
1.3 V
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3V
1.3 V
0V
th
3V
1.3 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.3 V
tw
1.3 V
Low-Level
Pulse
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
Output
Control
(low-level
enabling)
tPZL
Waveform 1
(see Notes C
and D)
tPZH
VOH
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Waveform 2
(see Notes C
and D)
3V
1.3 V
1.3 V
0V
tPLZ
≈1.5
V
VOL
tPHZ
VOH
1.3 V
VOH − 0.5 V
≈1.5
V
VOL + 0.5 V
3V
Input
1.3 V
1.3 V
0V
tPLH
In-Phase
Output
(see Note D)
tPHL
Out-of-Phase
Output
(see Note D)
1.3 V
tPHL
VOH
1.3 V
VOL
tPLH
1.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, ZO
≈
50
Ω,
tr
≤
1.5 ns, tf
≤
2.6 ns.
G. The outputs are measured one at a time, with one input transition per measurement.
Figure 2. Load Circuits and Voltage Waveforms
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DALLAS, TEXAS 75265
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