SN65LVDS1
SN65LVDS2
SN65LVDT2
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SLLS373H–JULY 1999–REVISED JULY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION CONTINUED
When the SN65LVDS1 is used with an LVDS receiver (such as the SN65LVDT2) in a point-to-point connection,
data or clocking signals can be transmitted over printed-circuit-board traces or cables at very high rates with
very low electromagnetic emissions and power consumption. The packaging, low power, low EMI, high ESD
tolerance, and wide supply voltage range make the device ideal for battery-powered applications.
The SN65LVDS1, SN65LVDS2, and SN65LVDT2 are characterized for operation from –40°C to 85°C.
FUNCTION TABLES
DRIVER
RECEIVER
INPUT
D
OUTPUTS
INPUTS
OUTPUT
Y
Z
V
= V − V
B
R
H
ID
A
H
L
H
L
L
L
H
H
V
≥ 100 mV
ID
−100 mV < V < 100 mV
?
L
H
ID
Open
V
≤ −100 mV
ID
Open
H = high level, L = low level , ? = indeterminate
DRIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
V
CC
V
CC
50 Ω
D Input
5 Ω
Y or Z
Output
10 kΩ
7 V
300 kΩ
7 V
RECEIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
V
CC
V
CC
300 kΩ
300 kΩ
5 Ω
R Output
A Input
B Input
7 V
7 V
7 V
110-Ω LVDT Only
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