ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊꢋ ꢌ ꢀ ꢁꢍ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊ ꢋ
ꢃ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢃꢋ
ꢌ
ꢀ
ꢁ
ꢂ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢉ
ꢋ
www.ti.com
SLLS562C − MARCH 2003 − REVISED − JUNE 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
(1) (2)
over operating free-air temperature range unless otherwise noted
UNITS
Supply voltage range, V
Voltage range at A or B
−0.5 V to 7 V
−9 V to 14 V
CC
Voltage range at any logic pin
Receiver output current
−0.3 V to V
+ 0.3 V
CC
−24 mA to 24 mA
Voltage input range, transient pulse, A and B, through 100 Ω (see Figure 13)
Junction temperature, T
−50 V to 50 V
170°C
J
Continuous total power dissipation
Refer to Package Dissipation Table
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functionaloperation of the device at these or any other conditions beyond those indicated under recommendedoperating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
PACKAGE DISSIPATION RATINGS
(3)
DERATING FACTOR
T
<25°C
T
= 70°C
T = 85°C
A
POWER RATING
A
A
PACKAGE
JEDEC BOARD MODEL
POWER RATING
ABOVE T = 25°C
POWER RATING
A
(1)
Low k
507 mW
4.82 mW/°C
7.85 mW/°C
6.53 mW/°C
3.76 mW/°C
5.55 mW/°C
289 mW
217 mW
D
P
(2)
High k
824 mW
471 mW
353 mW
(1)
Low k
686 mW
392 mW
294 mW
(1)
Low k
394 mW
255 mW
169 mW
DGK
(2)
High k
583 mW
333 mW
250 mW
(1)
(2)
(3)
In accordance with the low-k thermal metric definitions of EIA/JESD51-3
In accordance with the high-k thermal metric definitions of EIA/JESDS1-7
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
2
TI [ TEXAS INSTRUMENTS ]
