SLLS562G – AUGUST 2009 – REVISED MAY 2009
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
Supply voltage range, V
CC
Voltage range at A or B
Voltage range at any logic pin
Receiver output current
Voltage input, transient pulse, A and B, through 100
Ω.
See
Junction Temperature, T
J
Continuous total power dissipation
(1)
(2)
(2)
UNIT
–0.5 V to 7 V
–9 V to 14 V
–0.3 V to V
CC
+ 0.3 V
–24 mA to 24 mA
–50 to 50 V
170°C
See the Package Dissipation Table
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
PACKAGE DISSIPATION RATINGS
PACKAGE
D
P
DGK
(1)
(2)
(3)
JEDEC BOARD
MODEL
Low k
(2)
High k
(3)
Low k
(2)
T
A
< 25°C
POWER RATING
507 mW
824 mW
686 mW
394 mW
583 mW
DERATING FACTOR
ABOVE T
A
= 25°C
4.82 mW/°C
7.85 mW/°C
6.53 mW/°C
3.76 mW/°C
5.55 mW/°C
(1)
T
A
= 70°C
POWER RATING
289 mW
471 mW
392 mW
255 mW
333 mW
T
A
= 85°C
POWER RATING
217 mW
353 mW
294 mW
169 mW
250 mW
Low k
(2)
High k
(3)
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
In accordance with the low-k thermal metric definitions of EIA/JESD51-3
In accordance with the high-k thermal metric definitions of EIA/JESD51-7
2
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