SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101D – JULY 1985 – REVISED APRIL 2003
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
†
‡
PARAMETER
Input clamp voltage
TEST CONDITIONS
MIN
TYP
MAX
–1.5
6
UNIT
V
V
I = –18 mA
V
V
V
IK
I
Output voltage
I
= 0
= 0
0
O
O
O
|V
|
|
Differential output voltage
I
1.5
3.6
2.5
6
OD1
OD2
OD3
1/2 V
OD1
R
= 100 Ω,
= 54 Ω,
See Figure 1
See Figure 1
L
L
¶
or 2
|V
Differential output voltage
Differential output voltage
V
R
1.5
1.5
5
5
V
See Note 5
V
V
Change in magnitude
of differential output voltage
∆|V
|
|
R
R
R
= 54 Ω or 100 Ω, See Figure 1
= 54 Ω or 100 Ω, See Figure 1
= 54 Ω or 100 Ω, See Figure 1
±0.2
OD
OC
L
L
L
§
+3
–1
V
OC
Common-mode output voltage
V
V
Change in magnitude
of common-modeoutput voltage
∆|V
±0.2
§
V
V
= 12 V
1
–0.8
20
Output disabled,
See Note 6
O
I
Output current
mA
O
= –7 V
O
I
I
High-level input current
Low-level input current
V = 2.4 V
I
µA
µA
IH
V = 0.4 V
I
–400
–250
–150
250
250
70
IL
V
O
V
O
V
O
V
O
= –7 V
= 0
I
Short-circuit output current
mA
mA
OS
CC
= V
CC
= 12 V
Outputs enabled
Outputs disabled
42
26
I
Supply current (total package)
No load
35
†
Thepower-off measurement in ANSI Standard TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs.
‡
§
All typical values are at V
= 5 V and T = 25°C.
CC
A
∆|V
OD
level.
| and ∆|V
| are the changes in magnitude of V
and V
, respectively, that occur when the input is changed from a high level to a low
OC
OD
OC
¶
The minimum V
with a 100-Ω load is either 1/2 V
OD1
or 2 V, whichever is greater.
OD2
NOTES: 5. See ANSI Standard TIA/EIA-485-A, Figure 3.5, Test Termination Measurement 2.
6. This applies for both power on and off; refer to ANSI Standard TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does
not apply for a combined driver and receiver terminal.
switching characteristics, V
= 5 V, R = 110 Ω, T = 25°C (unless otherwise noted)
CC
L
A
PARAMETER
TEST CONDITIONS
MIN
TYP
15
MAX
22
UNIT
ns
t
t
t
t
t
t
Differential-output delay time
R
R
= 54 Ω,
See Figure 3
See Figure 3
d(OD)
t(OD)
PZH
PZL
L
L
Differential-output transition time
Output enable time to high level
Output enable time to low level
Output disable time from high level
Output disable time from low level
= 54 Ω,
20
30
ns
See Figure 4
See Figure 5
See Figure 4
See Figure 5
85
120
60
ns
40
ns
150
20
250
30
ns
PHZ
PLZ
ns
5
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