SDAS138B – DECEMBER 1983 – REVISED JANUARY 1995
D OR N PACKAGE
(TOP VIEW)
• Parallel-to-Serial, Serial-to-Parallel
Conversions
• Parallel Synchronous Loading
• J and K Inputs to First Stage
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
J
V
CC
Q
Q
Q
Q
Q
A
B
C
D
D
• Right Shift Only With Complementary
K
A
B
C
Outputs on Last Stage
• Direct Overriding Clear
• Package Options Include Plastic
Small-Outline (D) Packages and Standard
Plastic (N) 300-mil DIPs
D
CLK
SH/LD
GND
description
This 4-bit bidirectional universal shift register features parallel (A, B, C, D) inputs, parallel (Q , Q , Q , Q , Q )
A
B
C
D
D
outputs, J-K serial (J, K) inputs, shift/load control (SH/LD) input, and a direct overriding clear (CLR). The
registers have two modes of operation:
•
•
Parallel (broadside) load
Shift (in the direction Q toward Q )
A
D
Parallel loading is accomplished by applying the four bits of data and taking SH/LD low. The data is loaded into
the associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During
loading, serial data flow is inhibited.
Shifting is accomplished synchronously when SH/LD is high. Serial data for this mode is entered at the J-K
inputs. These inputs permit the first stage to perform as a J-K, D-, or T-type flip-flop as shown in the function
table.
The SN74AS195 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
SERIAL
OUTPUTS
PARALLEL
CLK
CLR
SH/LD
Q
Q
Q
Q
Q
D
A
B
C
D
J
X
X
X
L
A
X
a
B
X
C
X
c
D
X
d
K
X
X
X
H
L
L
X
L
X
↑
L
↑
↑
↑
↑
L
L
L
L
H
H
H
H
H
H
H
b
a
bc
d
d
H
H
H
H
H
X
X
X
X
X
XX
X
X
X
X
X
X
Q
Q
Q
C0
Q
Bn
Q
Bn
Q
Bn
Q
Bn
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
A0
A0
B0
A0
An
An
An
D0
Cn
Cn
Cn
Cn
D0
Cn
Cn
Cn
Cn
X
X
X
X
Q
Q
Q
Q
Q
L
X
L
H
H
H
L
X
H
X
Q
AN
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TI [ TEXAS INSTRUMENTS ]
