Functional Overview
3.1
Memory Map
Block
On-Chip Memory
External Memory XINTF
Start Address
Data Space
Prog Space
Data Space
Prog Space
0x00 0000
M0 Vector − RAM (32 × 32)
(Enabled if VMAP = 0)
0x00 0040
0x00 0400
M0 SARAM (1K × 16)
M1 SARAM (1K × 16)
0x00 0800
0x00 0D00
Peripheral Frame 0
Reserved
(2K × 16)
PIE Vector - RAM
(256 × 16)
(Enabled if VMAP
Reserved
= 1, ENPIE = 1)
0x00 0E00
0x00 2000
Reserved
0x00 2000
0x00 4000
XINTF Zone 0 (8K × 16, XZCS0AND1)
XINTF Zone 1 (8K × 16, XZCS0AND1) (Protected)
Reserved
0x00 6000
0x00 7000
Peripheral Frame 1
(4K × 16, Protected)
Reserved
Peripheral Frame 2
(4K × 16, Protected)
Reserved
0x00 8000
0x00 9000
0x00 A000
L0 SARAM (4K × 16, Secure Block)
L1 SARAM (4K × 16, Secure Block)
0x08 0000
0x10 0000
0x18 0000
XINTF Zone 2 (0.5M × 16, XZCS2)
XINTF Zone 6 (0.5M × 16, XZCS6AND7)
Reserved
0x3D 7800
OTP (or ROM) (1K × 16, Secure Block)
0x3D 7C00
0x3D 8000
0x3F 7FF8
Reserved (1K)
Reserved
Flash (or ROM) (128K × 16, Secure Block)
128-Bit Password
0x3F 8000
0x3F A000
H0 SARAM (8K × 16)
Reserved
0x3F C000
0x3F F000
0x3F FFC0
XINTF Zone 7 (16K × 16, XZCS6AND7)
Boot ROM (4K × 16)
(Enabled if MP/MC = 0)
(Enabled if MP/MC = 1)
XINTF Vector - RAM (32 × 32)
(Enabled if VMAP = 1, MP/MC = 1, ENPIE = 0)
BROM Vector - ROM (32 × 32)
(Enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
LEGEND:
Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.
NOTES: A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC, not in both.
D. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
E. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
F. Certain memory ranges are EALLOW protected against spurious writes after configuration.
G. Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations.
Figure 3−2. F2812 Memory Map (See Notes A through E)
16
SGUS053B
December 2004 − Revised September 2006
TI [ TEXAS INSTRUMENTS ]
