SPNS174
–
SEPTEMBER 2011
4.5
4.5.1
ARM
©
Cortex-R4F™ CPU Information
Summary of ARM Cortex-R4F™ CPU Features
The features of the ARM Cortex-R4F™ CPU include:
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An integer unit with integral EmbeddedICE-RT logic.
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High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI)
for Level two (L2) master and slave interfaces.
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Floating Point Coprocessor
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Dynamic branch prediction with a global history buffer, and a 4-entry return stack
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Low interrupt latency.
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Non-maskable interrupt.
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A Harvard Level one (L1) memory system with:
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Tightly-Coupled Memory (TCM) interfaces with support for error correction or parity checking
memories
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ARMv7-R architecture Memory Protection Unit (MPU) with 12 regions
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Dual core logic for fault detection in safety-critical applications.
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An L2 memory interface:
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Single 64-bit master AXI interface
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64-bit slave AXI interface to TCM RAM blocks
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A debug interface to a CoreSight Debug Access Port (DAP).
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A trace interface to a CoreSight ETM-R4.
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A Performance Monitoring Unit (PMU).
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A Vectored Interrupt Controller (VIC) port.
For more information on the ARM Cortex-R4F™ CPU please see
Figure 4-2. Dual - CPU Orientation
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System Information and Electrical Specifications
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©
2011, Texas Instruments Incorporated
F
PRODUCT PREVIEW
4.5.2
ARM Cortex-R4F™ CPU Features Enabled by Software
The following CPU features are disabled on reset and must be enabled by the application if required.
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ECC On Tightly-Coupled Memory (TCM) Accesses
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Harware Vectored Interrupt (VIC) Port
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Floating Point Coprocessor
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Memory Protection Unit (MPU)
4.5.3
Dual Core Implementation
The device has two Cortex-R4F cores, where the output signals of both CPUs are compared in the
CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by 2
clock cycles as shown in
The CPUs have a diverse CPU placement given by following requirements:
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different orientation; e.g. CPU1 = "north" orientation, CPU2 = "flip west" orientation
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dedicated guard ring for each CPU
North
Flip West
F