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RM48L550PGET 参数 Datasheet PDF下载

RM48L550PGET图片预览
型号: RM48L550PGET
PDF下载: 下载PDF文件 查看货源
内容描述: RM48Lx50 16位/ 32位RISC闪存微控制器 [RM48Lx50 16/32-Bit RISC Flash Microcontroller]
分类和应用: 闪存微控制器
文件页数/大小: 157 页 / 2926 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SPNS174
SEPTEMBER 2011
4.5
4.5.1
ARM
©
Cortex-R4F™ CPU Information
Summary of ARM Cortex-R4F™ CPU Features
The features of the ARM Cortex-R4F™ CPU include:
An integer unit with integral EmbeddedICE-RT logic.
High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI)
for Level two (L2) master and slave interfaces.
Floating Point Coprocessor
Dynamic branch prediction with a global history buffer, and a 4-entry return stack
Low interrupt latency.
Non-maskable interrupt.
A Harvard Level one (L1) memory system with:
Tightly-Coupled Memory (TCM) interfaces with support for error correction or parity checking
memories
ARMv7-R architecture Memory Protection Unit (MPU) with 12 regions
Dual core logic for fault detection in safety-critical applications.
An L2 memory interface:
Single 64-bit master AXI interface
64-bit slave AXI interface to TCM RAM blocks
A debug interface to a CoreSight Debug Access Port (DAP).
A trace interface to a CoreSight ETM-R4.
A Performance Monitoring Unit (PMU).
A Vectored Interrupt Controller (VIC) port.
For more information on the ARM Cortex-R4F™ CPU please see
Figure 4-2. Dual - CPU Orientation
56
System Information and Electrical Specifications
focus.ti.com:
Copyright
©
2011, Texas Instruments Incorporated
F
PRODUCT PREVIEW
4.5.2
ARM Cortex-R4F™ CPU Features Enabled by Software
The following CPU features are disabled on reset and must be enabled by the application if required.
ECC On Tightly-Coupled Memory (TCM) Accesses
Harware Vectored Interrupt (VIC) Port
Floating Point Coprocessor
Memory Protection Unit (MPU)
4.5.3
Dual Core Implementation
The device has two Cortex-R4F cores, where the output signals of both CPUs are compared in the
CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by 2
clock cycles as shown in
The CPUs have a diverse CPU placement given by following requirements:
different orientation; e.g. CPU1 = "north" orientation, CPU2 = "flip west" orientation
dedicated guard ring for each CPU
North
Flip West
F