SPNS174
–
SEPTEMBER 2011
3.5
Power Consumption Over Recommended Operating Conditions
PARAMETER
TEST CONDITIONS
f
HCLK
= 200MHz
V
CC
digital supply current (operating mode)
f
VCLK
= 100MHz,
Flash in pipelined
mode, V
CCmax
LBIST clock rate =
100MHz
PBIST ROM clock
frequency = 100MHz
V
CCPLL
= V
CCPLLmax
No DC load, V
CCmax
Single ADC
operational,
V
CCADmax
Both ADCs
operational,
V
CCADmax
Single ADC
operational,
AD
REFHImax
Both ADCs
operational,
AD
REFHImax
read operation
V
CCPmax
program, V
CCPmax
read from 1 bank
and program
another bank,
V
CCPmax
erase, V
CCPmax
TBD
10
15
15
mA
mA
MIN
TYP
MAX
UNIT
I
CC
V
CC
Digital supply current (LBIST mode)
VCC Digital supply current
(PBIST mode)
I
CCPLL
I
CCIO
Peak
RMS
mA
mA
mA
mA
VCCPLL digital supply current (operating mode)
V
CCIO
Digital supply current (operating mode.
I
CCAD
V
CCAD
supply current (operating mode)
30
5
mA
PRODUCT PREVIEW
I
CCREFHI
AD
REFHI
supply current (operating mode)
10
34
37
55
mA
I
CCP
V
CCP
pump supply current
27
46
Device Operating Conditions
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2011, Texas Instruments Incorporated
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