SPNS174
–
SEPTEMBER 2011
5.10.2 Management Data Input/Output (MDIO)
1
3
MDCLK
4
5
MDIO
(input)
3
Figure 5-19. MDIO Input Timing
Table 5-25. MDIO Input Timing Requirements
NO.
1
2
3
4
5
tc(MDCLK)
tw(MDCLK)
tt(MDCLK)
tsu(MDIO-MDCLKH)
th(MDCLKH-MDIO)
Parameter
MIN
Cycle time, MDCLK
Pulse duration, MDCLK high/low
Transition time, MDCLK
Setup time, MDIO data input valid before MDCLK
High
Hold time, MDIO data input valid after MDCLK
High
400
180
-
10
10
Value
MAX
-
-
5
-
-
ns
ns
ns
ns
ns
Unit
1
MDCLK
7
MDIO
(output)
Figure 5-20. MDIO Output Timing
Table 5-26. MDIO Output Timing Requirements
NO.
1
7
tc(MDCLK)
td(MDCLKL-MDIO)
Parameter
MIN
Cycle time, MDCLK
Delay time, MDCLK low to MDIO data output
valid
400
0
Value
MAX
-
100
ns
ns
Unit
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©
2011, Texas Instruments Incorporated
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