SPNS174
–
SEPTEMBER 2011
5 Peripheral Information and Electrical Specifications
5.1
Peripheral Legend
Table 5-1. Peripheral Legend
Abbreviation
MibADC
CCM-R4F
CRC
DCAN
DCC
DMA
DMM
EMIF
ESM
ETM-R4F
GIO
HTU
I2C
LIN
MIBSPI
N2HET
POM
RTI
RTP
SCI
SPI
USB
VIM
Full Name
Analog To Digital Converter
CPU Compare Module - CortexR4F
Cyclic Redundancy Check
Controller Area Network
Dual Clock Comparator
Direct Memory Access
Data Modification Module
External Memory Interface
Error Signaling Module
Embedded Trace Macrocell - CortexR4F
General-Purpose Input/Output
High End Timer Transfer Unit
Inter-Integrated Circuit
Local Interconnect Network
Multibuffer Serial Peripheral Interface
Platform High-End Timer
Parameter Overlay Module
Real-Time Interrupt Module
RAM Trace Port
Serial Communications Interface
Serial Peripheral Interface
Universal Serial Bus
Vectored Interrupt Manager
5.2
Multi-Buffered 12bit Analog-to-Digital Converter
The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that
enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could
be present on V
SS
and V
CC
from coupling into the A-to-D analog stage. All A-to-D specifications are given
with respect to AD
REFLO
unless otherwise noted.
Table 5-2. MibADC Overview
Description
Resolution
Monotonic
Output conversion code
Value
12 bits
Assured
00h to FFFh [00 for V
AI
≤
AD
REFLO
; FFF for V
AI
≥
AD
REFHI
]
5.2.1
•
•
•
•
•
•
Features
10-/12-bit resolution
AD
REFHI
and AD
REFLO
pins (high and low reference voltages)
Total Sample/Hold/Convert time: 600ns Typical Minimum at 30MHz ADCLK
One memory region per conversion group is available (event, group 1, group 2)
Allocation of channels to conversion groups is completely programmable
Memory regions are serviced either by interrupt or by DMA
Peripheral Information and Electrical Specifications
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©
2011, Texas Instruments Incorporated
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