SPNS174
–
SEPTEMBER 2011
4.21 Debug Subsystem
4.21.1 Block Diagram
The device contains an ICEPICK module to allow JTAG access to the scan chains.
Boundary Scan I/F
TRST
TMS
TCK
RTCK
TDI
TDO
Boundary Scan
BSR/BSDL
Debug APB
Debug
ROM1
Secondary Tap 0
DAP
APB Mux
AHB-AP
POM
to SCR1 via A2A
from
PCR1/Bridge
APB slave
Cortex
R4F
ETM
TPIU
ICEPICK_C
PRODUCT PREVIEW
RTP
Secondary Tap 1
TAP 0
DMM
TAP 1
Secondary Tap 2
AJSM
Figure 4-19. ZWT Debug Subsystem Block Diagram
4.21.2 Debug Components Memory Map
Table 4-37. Debug Components Memory Map
MODULE NAME
CoreSight Debug
ROM
Cortex-R4F
Debug
ETM-R4
CoreSight TPIU
FRAME CHIP
SELECT
CSCS0
CSCS1
CSCS2
CSCS3
FRAME ADDRESS RANGE
START
0xFFA0_0000
0xFFA0_1000
0xFFA0_2000
0xFFA0_3000
END
0xFFA0_0FFF
0xFFA0_1FFF
0xFFA0_2FFF
0xFFA0_3FFF
FRAME ACTUA
SIZE
L SIZE
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
RESPNSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
106
System Information and Electrical Specifications
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