RM46L450
RM46L850
SPNS184 –SEPTEMBER 2012
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4.3 Power Sequencing and Power On Reset
4.3.1 Power-Up Sequence
There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-
up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 4-4 for
more details), core voltage rising above the minimum core supply threshold and the release of power-on
reset. The high frequency oscillator will start up first and its amplitude will grow to an acceptable level. The
oscillator start up time is dependent on the type of oscillator and is provided by the oscillator vendor. The
different supplies to the device can be powered up in any order.
The device goes through the following sequential phases during power up.
Table 4-3. Power-Up Phases
Oscillator start-up and validity check
eFuse autoload
1032 oscillator cycles
1160 oscillator cycles
688 oscillator cycles
617 oscillator cycles
3497 oscillator cycles
Flash pump power-up
Flash bank power-up
Total
The CPU reset is released at the end of the above sequence and fetches the first instruction from address
0x00000000.
4.3.2 Power-Down Sequence
The different supplies to the device can be powered down in any order.
4.3.3 Power-On Reset: nPORRST
This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core
supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an
internal pulldown.
4.3.3.1 nPORRST Electrical and Timing Requirements
Table 4-4. Electrical Requirements for nPORRST
NO Parameter
MIN
MAX
Unit
VCCPORL
VCC low supply level when nPORRST must be active during power-
up
0.5
V
VCCPORH
VCC high supply level when nPORRST must remain active during
power-up and become active during power down
1.14
V
V
V
VCCIOPORL
VCCIOPORH
VIL(PORRST)
VCCIO / VCCP low supply level when nPORRST must be active during
power-up
1.1
VCCIO / VCCP high supply level when nPORRST must remain active
during power-up and become active during power down
3.0
Low-level input voltage of nPORRST VCCIO > 2.5V
Low-level input voltage of nPORRST VCCIO < 2.5V
0.2 * VCCIO
0.5
V
V
3
tsu(PORRST)
Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL
during power-up
0
ms
6
7
th(PORRST)
tsu(PORRST)
Hold time, nPORRST active after VCC > VCCPORH
1
2
ms
µs
Setup time, nPORRST active before VCC < VCCPORH during power
down
8
9
th(PORRST)
th(PORRST)
Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH
Hold time, nPORRST active after VCC < VCCPORL
1
0
ms
ms
56
System Information and Electrical Specifications
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