RM46L450
RM46L850
SPNS184 –SEPTEMBER 2012
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Table 5-21. MibADC Timing Specifications
Parameter
Cycle time, MibADC clock
MIN
0.033
0.2
NOM
MAX
Unit
µs
(1)
tc(ADCLK)
(2)
td(SH)
Delay time, sample and hold
time
µs
12-bit mode
td©)
Delay time, conversion time
0.4
0.6
µs
µs
(3)
td(SHC)
Delay time, total sample/hold
and conversion time
10-bit mode
td©)
Delay time, conversion time
0.33
0.53
µs
µs
(3)
td(SHC)
Delay time, total sample/hold
and conversion time
(1) The MibADC clock is the ADCLK, generated by dividing down the VCLK by a prescale factor defined by the ADCLOCKCR register bits
4:0.
(2) The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the AD<GP>SAMP register for each
conversion group. The sample time needs to be determined by accounting for the external impedance connected to the input channel as
well as the ADC’s internal impedance.
(3) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, e.g the
prescale settings.
132
Peripheral Information and Electrical Specifications
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