RM46L450
RM46L850
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SPNS184 –SEPTEMBER 2012
5 Peripheral Information and Electrical Specifications
5.1 Enhanced Translator PWM Modules (ePWM)
Figure 5-1 illustrates the connections between the seven ePWM modules (ePWM1,2,3,4,5,6,7) on the
device.
PINMMR36[25]
NHET1_LOOP_SYNC
EPWMSYNCI
EPWM1A
EPWM1TZINTn
EPWM1INTn
VIM
VIM
EPWM1B
TZ1/2/3n
Mux
Selector
SOCA1, SOCB1
ADC Wrapper
EPWM1
VBus32
EQEP1ERR / EQEP2ERR /
EQEP1ERR or EQEP2ERR
OSC FAIL or PLL Slip
EQEP1 + EQEP2
System Module
CPU
TZ4n
VCLK4, SYS_nRST
EPWM1ENCLK
TBCLKSYNC
TZ5n
TZ6n
Debug Mode Entry
EPWM2/3/4/5/6A
EPWM2/3/4/5/6B
EPWM2/3/4/5/6TZINTn
EPWM2/3/4/5/6INTn
VIM
VIM
TZ1/2/3n
ADC Wrapper
Mux
Selector
SOCA2/3/4/5/6
SOCB2/3/4/5/6
EPWM
2/3/4/5/6
VBus32
EQEP1ERR / EQEP2ERR /
EQEP1ERR or EQEP2ERR
OSC FAIL or PLL Slip
EQEP1 + EQEP2
System Module
CPU
TZ4n
VCLK4, SYS_nRST
EPWM2/3/4/5/6ENCLK
TBCLKSYNC
TZ5n
TZ6n
Debug Mode Entry
EPWM7A
EPWM7TZINTn
EPWM7INTn
VIM
VIM
EPWM7B
TZ1/2/3n
Mux
Selector
SOCA7, SOCB7
ADC Wrapper
EPWM
7
VBus32
EQEP1ERR / EQEP2ERR /
EQEP1ERR or EQEP2ERR
OSC FAIL or PLL SLip
EQEP1 + EQEP2
System Module
CPU
TZ4n
TZ5n
TZ6n
VCLK4, SYS_nRST
EPWM7ENCLK
TBCLKSYNC
Debug Mode Entry
Pulse
Stretch,
8 VCLK4
cycles
EPWMSYNCO
ECAP1
VBus32 / VBus32DP
ECAP
1
ECAP1INTn
VIM
Figure 5-1. ePWMx Module Interconnections
Copyright © 2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
117
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