PTH12030W/L
www.ti.com
SLTS211F–MAY 2003–REVISED FEBRUARY 2007
Table 6. Margin Up/Down Resistor Values
% ADJUST
RU / RD
0 kΩ
5
4
3
2
1
24.9 kΩ
66.5 kΩ
150 kΩ
397 kΩ
10
9
8
1
2
7
6
+VO
0 V
PTH12010W
(Top View)
+VO
VI
3
4
5
RD
RU
+
RSET
+
CI
Margin Down
Margin Up
0.1 W, 1 %
L
CO
Q1
O
A
D
Q2
GND
GND
Figure 20. Margin Up/Down Application Schematic
MARGIN UP/DOWN NOTES
1. The Margin Up and Margin Down controls were not intended to be activated simultaneously. If they are
their affects on the output voltage may not completely cancel, resulting in the possibility of a slightly
higher error in the output voltage set point.
2. The ground reference should be a direct connection to the module GND at pin 7 (pin 1 for the
PTHxx050). This will produce a more accurate adjustment at the load circuit terminals. The transistors Q1
and Q2 should be located close to the regulator.
3. The Margin Up and Margin Down control inputs are not compatible with devices that source voltage. This
includes TTL logic. These are analog inputs and should only be controlled with a true open-drain device
(preferably discrete MOSFET transistor). The device selected should have low off-state leakage current.
Each input sources 8 µA when grounded, and has an open-circuit voltage of 0.8 V.
20
Submit Documentation Feedback
TI [ TEXAS INSTRUMENTS ]
