PTH12030W/L
www.ti.com
SLTS211F–MAY 2003–REVISED FEBRUARY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
STANDARD APPLICATION
Margin Down
Margin Up
Track
13 12 11
1
2
3
10
V
I
9
8
PTH12030x
(Top View)
V
O
7
4
5
6
Inhibit
V
Sense
O
L
O
A
D
C
I
C
O
560 mF
Electrolytic
(Required)
330 mF
(Optional)
R
SET
GND
GND
A. RSET = Required to set the output voltage to a value higher than the minimum value. See the Application Information
section for values.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see
the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range, all voltages are with respect to GND (unless otherwise noted)
MIN
–0.3
–40
TYP
MAX
VI + 0.3
85
UNIT
V
VTrack Track pin voltage
TA Operating Temperature
Range
Over VI range
°C
(1)
Twave Wave solder temperature Surface temperature of module body or pins
PTH12030WAH
260
(5 seconds)
°C
(1)
PTH12030WAS
PTH12030WAZ
235
Treflow Solder reflow temperature Surface temperature of module body or pins
(1)
260
Tstg
Storage Temperature
Mechanical Shock
Mechanical Vibration
Weight
–55
125
°C
G
Per Mil-STD-883D, Method 2002.3, 1 ms, 1/2 Sine, mounted
500
Mil-STD-883D, Method 2007.2 20-2000 Hz
15
10
G
grams
Flammability
Meets UL 94V-O
(1) During soldering of package version, do not elevate peak temperature of the module, pins, or internal components above the stated
maximum.
2
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