Not Recommended for New Designs
ML (pin 18)
MC (pin 17)
MD (pin 16)
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
tMLS
tMLH
50% of VDD
ML
tMHH
tMCY
tMLL
tMCH
tMCL
MC
MD
50% of VDD
50% of VDD
tMDS
MC Pulse Cycle
MC Pulsewidth “L”
MC Pulse Cycle “H”
MD Setup Time
MD Hold Time
ML Setup Time
ML Hold Time
ML Pulsewidth “L”
ML High Level Time
tMDH
tMCY
tMCL
tMCH
tMDS
tMDH
tMLS
tMLH
tMLL
100ns (min)
50ns (min)
50ns (min)
30ns (min)
30ns (min)
30ns (min)
30ns (min)
30ns + 1SYSCLK (min)
30ns + 1SYSCLK (min)
tMHH
FIGURE 8. Control Data Timing in Software Mode Control.
50% of VDD
20ns (min)
RSTB
RSTB Pulsewidth
tRST
FIGURE 9. External Reset Timing.
0.1µF ~ 10µF
Bypass Capacitor
+5V Analog Power Supply
2
3
10pF ~ 22pF
DGND
XTI
VDD
FOUT = Inverted XTI (1 pin)
to Other System
1
CLKO 19
20 XTO
10pF ~ 22pF
Post
Low Pass
Filter
VOUT
R
9
8
4
5
6
LRCIN
D/C_R
(optional)
PCM
Audio Data
Processor
+
+
10µF
10µF
DIN
BCKIN
Post
Low Pass
Filter
Mode Control
14 MODE
D/C_L 13
OUTL 12
VDD
18 ML/MUTE
17 MC/DM1
16 MD/DM0
15 RSTB
V
(optional)
Control
Processor
4.7kΩ
ZERO
VCC
11
7
To External Mute Circuit
AGND
10
Reset
0.1µF ~ 10µF
Bypass Capacitor
FIGURE 10. Typical Connection Diagram of PCM1717.
®
11
PCM1717
TI [ TEXAS INSTRUMENTS ]
