2 Terminal Descriptions
The PCI6x21/PCI6x11 controller is available in the 288-terminal MicroStar BGA package (GHK) or the 288-terminal
lead-free (Pb, atomic number 82) MicroStar BGA package (ZHK). Figure 2−1 is a pin diagram of the PCI6621
package. Figure 2−2 is a pin diagram of the PCI6421 package. Figure 2−3 is a pin diagram of the PCI6611 package.
Figure 2−4 is a pin diagram of the PCI6411 package.
AD27
AD29
VCCP C/BE3 IDSEL
AD19
C/BE2 STOP C/BE1 VCCP C/BE0
AD4
AD3
AD2
AD0
RSVD RSVD RSVD
NC
RSVD
W
V
U
T
VDPLL_
33
AD30
REQ
AD26
AD28
AD24
AD25
AD23
AD22
AD18 FRAME PERR
AD15
AD14
AD11
AD10
AD7
AD6
RSVD RSVD RSVD AVDD RSVD
RSVD
RSVD
AD31
AD17
IRDY
SERR
AGND RSVD AGND RSVD RSVD RSVD
VDPLL_
15
RI_OUT
//PME
RSVD
RSVD
GRST
MFUNC6
GNT
VSSPLL
PHY_
TEST_
MA
RSVD
SUSPEND
RSVD
TEST0
AGND
VCC
PRST
AD21
AD20
AD16
TRDY
AD13
PAR
AD9
AD5
AVDD
AVDD
R
P
N
M
L
B_CAD1
//B_D4
B_CAD0
//B_D3
B_CAD2
//B_D11
MFUNC2 MFUNC3 MFUNC4
PCLK
MFUNC5
MFUNC1
VSSPLL RSVD
B_CCD1
//B_CD1
B_CAD5
//B_D6
B_CAD4
//B_D12
B_RSVD
//B_D14
B_CAD6
//B_D13
MFUNC0
SCL
DATA LATCH
VCC DEVSEL AD12
AD8
VCC
GND
GND
GND
VCC
AD1
RSVD
GND
GND
GND
VCC
B_CC/BE0
//B_CE1
B_CAD9
//B_A10
VR_
PORT
B_CAD3 B_CAD8
B_CAD7
//B_D7
CLK_48
VCC
GND
GND
VCC
SDA
//B_D5
//B_D15
SC_
PWR_
CTRL
B_CAD15
//B_IOWR
B_CAD13
//B_IORD
B_CAD11 B_CAD10
//B_OE //B_CE2
B_CAD12
//B_A11
SC_
DATA
SPKROUT
SC_CD SC_OC
CLOCK
GND
GND
GND
SM_R/B
//
SM_ PHYS
_WP//
SC_
VCC_
5V
B_CPAR
//B_A13
B_RSVD
//B_A18
B_CC/BE1
//B_A8
B_CAD16
//B_A17
B_CAD14
VCCB
SC_RST
VCC
VCC
VCC
GND
VCC
VCC
K
J
SC_CLK
//B_A9
SC_RFU
SC_FCB
SD_DAT2 SD_DAT3
//SM_D6// //SM_D7//
SC_GPIO4 SC_GPIO3
SD_CMD//
SM_ALE//
SC_GPIO2
SD_DAT1//
SM_D5//
SD_CLK//
SM_RE//
B_CIRDY
//B_A15
B_CPERR B_CBLOCK
SM_CLE//
SC_GPIO0
B_CGNT
//B_WE
B_CSTOP
//B_A20
GND
VCC
//B_A19
//B_A14
SC_GPIO1
SC_GPIO5
MS_DATA3
//SD_DAT3
//SM_D3
SD_DAT0//
SM_D4//
B_CAD18
//B_A7
B_CDEVSEL
//B_A21
B_CTRDY
//B_A22
SD_WP//
SM_CE
VR_
B_CAD19
//B_A25
B_CCLK
//B_A16
VR_EN
PORT
VCC
GND
GND
H
G
F
SC_GPIO6
MS_SDIO
MS_DATA1
(DATA0)//
MS_CLK//
SD_CLK//
MS_DATA2
//SD_DAT2
//SM_D2
B_CC/BE2
//B_A12
B_CAD17
//B_A24
B_CFRAME
//B_A23
A_CAD20 A_CPAR
A_CC/BE0
//A_CE1
B_CAD21
//B_A5
A_CAD14
//A_A9
GND
//SD_DAT1
SD_DAT0//
//A_A6
//A_A13
//SM_D1
SM_D0
SM_EL_WP
B_CSTSCHG
//B_BVD1
MS_BS//
SD_CMD
//SM_WE
B_CAD20
//B_A6
B_CVS2
//B_VS2
B_CRST
B_CC/BE3
//B_REG
MC_PWR MC_PWR
_CTRL_0 _CTRL_1
A_CAD6
//A_D13
A_CC/BE2
//A_A12
A_CPERR
//A_A14
MS_CD SM_CD
//B_RESET
(STSCHG/RI)
A_CVS2 A_CCLK
A_CREQ
A_CCD2
//A_CD2
A_CBLOCK
//A_A19
B_CREQ
A_CAD24
//A_A2
B_CAD23
//B_A3
A_CAD15
//A_IOWR
B_CAD22
//B_A4
A_CAD8
//A_D15
A_CAD0
//A_D3
A_CAD3
//A_D5
B_USB_EN A_USB_EN
SD_CD
E
D
C
B
A
//A_INPACK
//A_VS2
//A_A16
//B_INPACK
B_CAD24
//B_A2
A_RSVD A_CAD29
B_CAD26
//B_A0
A_CAD31
//A_D10
VCCB
//A_D1
//A_D2
A_CINT//
A_READY
(IREQ)
A_CCLKRUN
A_CAD28
B_CAUDIO
//B_BVD2
(SPKR)
A_CAD13
//A_IORD
B_CAD25
//B_A1
B_CVS1
//B_VS1
A_CDEVSEL A_RSVD
A_CAD30
//A_D9
A_CC/BE3 A_CAD22 A_CAD19
B_CAD27
//B_D0
A_CAD7
//A_D7
A_CAD4
//A_D12
A_CAD11
//A_OE
A_CFRAME
//A_A23
A_CCD1
//A_CD1
//A_WP
//A_D8
//A_A18
//A_A21
//A_REG
//A_A4
//A_A25
(IOIS16)
B_CINT
//B_READY
(IREQ)
A_CSTSCHG
A_CSERR
//A_BVD1
A_CAD26
//A_A0
A_CAD18
//A_A7
A_CAD27
//A_D0
B_CAD29
//B_D1
A_CAD23
//A_A3
A_CIRDY A_CGNT A_CC/BE1 A_CAD12 A_CAD10 A_RSVD
//A_A15 //A_WE //A_A11 //A_CE2 //A_D14
//A_A8
B_CAD31
//B_D10
B_CCD2
//B_CD2
B_CSERR
//B_WAIT
A_CAD21
//A_A5
A_CAD1
//A_D4
//A_WAIT
(STSCHG/RI)
A_CAUDIO
B_CCLKRUN
//B_WP
A_CAD2 B_RSVD
B_CAD30 B_CAD28
A_CSTOP A_CAD16
A_CAD5
//A_D6
A_CVS1 A_CAD25
A_CRST A_CAD17 A_CTRDY
A_CAD9
//A_A10
//A_BVD2
(SPKR)
VCCA
VCCA
//A_D11
//B_D2
//B_D9
//B_D8
//A_RESET
//A_A20
//A_A17
//A_VS1
//A_A1
//A_A24 //A_A22
(IOIS16)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Figure 2−1. PCI6621 GHK/ZHK-Package Terminal Diagram
2−1