SCPS131E – AUGUST 2005 – REVISED MAY 2008
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SCL
1
2
3
4
5
6
7
8
9
I0.x
I1.x
A
Acknowledge
From Master
10
A
Acknowledge
From Master
t
ps
I0.x
03
A
Acknowledge
From Master
No Acknowledge
From Master
I1.x
12
1
P
SDA
S
0
1
0
0
A2
A1
A0
1
A
Acknowledge
From Slave
t
ph
00
R/W
Read From Port 0
Data Into Port 0
Data 00
Data 01
t
ph
Data 02
Data 03
t
ps
Read From Port 1
Data Into Port 1
Data 10
Data 11
Data 12
INT
t
iv
t
ir
A.
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see
for these details).
B.
Figure 10. Read Input Port Register, Scenario 2
12
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