PCA9539
REMOTE 16-BIT I2C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
www.ti.com
SCPS130D–AUGUST 2005–REVISED MARCH 2007
1
2
3
4
5
6
7
8
9
SCL
SDA
I0.x
I1.x
I0.x
I1.x
3
S
1
1
1
0
1
A1 A0
1
A
7
6
5
4
3
2
1
0
A
7
6
5
4
3
2
1
0
A
7
6
5
4
3
2
1
0
A
7
6
5
4
2
1
0
1
P
Acknowledge
From Master
R/W
Acknowledge
From Master
Acknowledge
From Master
Acknowledge
From Slave
No Acknowledge
From Master
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
INT
t
t
ir
iv
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 8 for these details).
Figure 9. Read Input Port Register, Scenario 1
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1
2
3
4
5
6
7
8
9
SCL
I0.x
I1.x
I0.x
I1.x
S
1
1
1
0
1
A1 A0
1
A
00
A
10
A
03
A
1
P
SDA
12
Acknowledge
From Master
Acknowledge
From Master
Acknowledge
From Slave
Acknowledge
From Master
R/W
No Acknowledge
From Master
t
ps
t
ph
Read From Port 0
Data Into Port 0
Data 00
Data 01
Data 02
Data 03
t
t
ps
ph
Read From Port 1
11
12
Data
Data 10
Data
Data Into Port 1
INT
t
iv
t
ir
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 8 for these details).
Figure 10. Read Input Port Register, Scenario 2
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