INPUT BIAS CURRENT
Difet
fabrication of the OPA627/637 provides very low
input bias current. Since the gate current of a FET doubles
approximately every 10°C, to achieve lowest input bias
current, the die temperature should be kept as low as pos-
sible. The high speed and therefore higher quiescent current
of the OPA627/637 can lead to higher chip temperature. A
simple press-on heat sink such as the Burr-Brown model
807HS (TO-99 metal package) can reduce chip temperature
by approximately 15°C, lowering the I
B
to one-third its
warmed-up value. The 807HS heat sink can also reduce low-
frequency voltage noise caused by air currents and thermo-
electric effects. See the data sheet on the 807HS for details.
Temperature rise in the plastic DIP and SOIC packages can
be minimized by soldering the device to the circuit board.
Wide copper traces will also help dissipate heat.
The OPA627/637 may also be operated at reduced power
supply voltage to minimize power dissipation and tempera-
ture rise. Using
±5V
power supplies reduces power dissipa-
tion to one-third of that at
±15V.
This reduces the I
B
of TO-
99 metal package devices to approximately one-fourth the
value at
±15V.
Leakage currents between printed circuit board traces can
easily exceed the input bias current of the OPA627/637. A
circuit board “guard” pattern (Figure 4) reduces leakage
effects. By surrounding critical high impedance input cir-
cuitry with a low impedance circuit connection at the same
potential, leakage current will flow harmlessly to the low-
impedance node. The case (TO-99 metal package only) is
internally connected to –V
S
.
Input bias current may also be degraded by improper han-
dling or cleaning. Contamination from handling parts and
circuit boards may be removed with cleaning solvents and
deionized water. Each rinsing operation should be followed
by a 30-minute bake at 85°C.
Many FET-input op amps exhibit large changes in input
bias current with changes in input voltage. Input stage
cascode circuitry makes the input bias current of the
OPA627/637 virtually constant with wide common-mode
voltage changes. This is ideal for accurate high input-
impedance buffer applications.
PHASE-REVERSAL PROTECTION
The OPA627/637 has internal phase-reversal protection.
Many FET-input op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This
is most often encountered in non-inverting circuits when the
input is driven below –12V, causing the output to reverse
into the positive rail. The input circuitry of the OPA627/637
does not induce phase reversal with excessive common-
mode voltage, so the output limits into the appropriate rail.
OUTPUT OVERLOAD
When the inputs to the OPA627/637 are overdriven, the
output voltage of the OPA627/637 smoothly limits at ap-
proximately 2.5V from the positive and negative power
supplies. If driven to the negative swing limit, recovery
®
takes approximately 500ns. When the output is driven into
the positive limit, recovery takes approximately 6µs. Output
recovery of the OPA627 can be improved using the output
clamp circuit shown in Figure 5. Diodes at the inverting
input prevent degradation of input bias current.
+V
S
5kΩ
(2)
HP 5082-2811
ZD
1
1kΩ
5kΩ
R
F
V
I
R
I
–
+
OPA627
–V
S
V
O
Clamps output
at V
O
= ±11.5V
ZD
1
: 10V IN961
Diode Bridge
BB: PWS740-3
FIGURE 5. Clamp Circuit for Improved Overload Recovery.
CAPACITIVE LOADS
As with any high-speed op amp, best dynamic performance
can be achieved by minimizing the capacitive load. Since a
load capacitance presents a decreasing impedance at higher
frequency, a load capacitance which is easily driven by a
slow op amp can cause a high-speed op amp to perform
poorly. See the typical curves showing settling times as a
function of capacitive load. The lower bandwidth of the
OPA627 makes it the better choice for driving large capaci-
tive loads. Figure 6 shows a circuit for driving very large
load capacitance. This circuit’s two-pole response can also
be used to sharply limit system bandwidth. This is often
useful in reducing the noise of systems which do not require
the full bandwidth of the OPA627.
R
F
1kΩ
200pF
C
F
–
+
G = 1+
R
F
R
1
OPA627
R
1
R
O
20Ω
G = +1
BW
≥
1MHz
C
L
5nF
Optional Gain
Gain > 1
For Approximate Butterworth Response:
2 R
O
C
L
R
F
>> R
O
C
F
=
R
F
f
–3dB
=
1
2π
√
R
F
R
O
C
F
C
L
FIGURE 6. Driving Large Capacitive Loads.
OPA627, 637
10
TI [ TEXAS INSTRUMENTS ]
