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OPA129UBE4 参数 Datasheet PDF下载

OPA129UBE4图片预览
型号: OPA129UBE4
PDF下载: 下载PDF文件 查看货源
内容描述: 超低偏置电流Difet®运算放大器 [Ultra-Low Bias Current Difet® OPERATIONAL AMPLIFIER]
分类和应用: 运算放大器放大器电路光电二极管
文件页数/大小: 14 页 / 652 K
品牌: TI [ TEXAS INSTRUMENTS ]
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CIRCUIT BOARD LAYOUT
The OPA129 uses a new pinout for ultra low input bias
current. Pin 1 and pin 4 have no internal connection. This
allows ample circuit board space for a guard ring surround-
ing the op amp input pins—even with the tiny SO-8 surface-
mount package. Figure 3 shows suggested circuit board
layouts. The guard ring should be connected to pin 8 (sub-
strate) as shown. It should be driven by a circuit node equal
in potential to the input terminals of the op amp—see Figure
2 for common circuit configurations.
TESTING
Accurately testing the OPA129 is extremely difficult due to
its high performance. Ordinary test equipment may not be
able to resolve the amplifier’s extremely low bias current.
Inaccurate bias current measurements can be due to:
1. Test socket leakage.
2. Unclean package.
3. Humidity or dew point condensations.
4. Circuit contamination from fingerprints or anti-static
treatment chemicals.
5. Test ambient temperature.
6. Load power dissipation.
7. Mechanical stress.
8. Electrostatic and electromagnetic interference.
(A) Non-Inverting
(B) Buffer
1000MΩ
R
F
V+
I
IN
2
Current
Input
3
7
OPA129
8
5
V–
V
O
= –I
IN
• R
F
V
O
= –10V/nA
6
Output
2kΩ
18kΩ
FIGURE 4. Current-to-Voltage Converter.
500Ω
Guard
2
3
8
7
OPA129
5
V–
pH Probe
R
S
500MΩ
50mV Out
6
1VDC
Output
9.5kΩ
V+
FIGURE 5. High Impedance (10
15
Ω)
Amplifier.
C
F
10pF
10
11
2
3
In
8
6 Out
2
3
In
(C) Inverting
8
6
Out
R
F
V+
2
∆Q
3
8
7
6
Output
V
OUT
OPA129
5
In
2
6 Out
3
8
Low frequency cutoff =
V– 1/(2πR C ) = 0.16Hz
F F
V
OUT
= –∆Q/C
F
FIGURE 6. Piezoelectric Transducer Charge Amplifier.
Guard top and bottom of board.
FIGURE 2. Connection of Input Guard.
1
8
V+
V
0
V–
4
5
(A) DIP package
1
8
V+
V
0
4
5
V–
Connect to proper circuit
node, depending on circuit
configuration (see Figure 2).
Connect to proper circuit
node, depending on circuit
configuration (see Figure 2).
~1pF to prevent gain peaking
10
10
Guard
Pin photodiode
HP 5082-4204
2
3
+15V
8
OPA129
0.1µF
7
6
Output
5 x 10
9
V/W
5
0.1µF
–15V
Circuit must be well shielded.
(B) SOIC package
FIGURE 3. Suggested Board Layout for Input Guard.
FIGURE 7. Sensitive Photodiode Amplifier.
7
OPA129
SBOS026A
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