OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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6.22.2 LCD Raster Mode
Table 6-79. LCD Raster Mode Timing
See Figure 6-54 through Figure 6-58
NO.
PARAMETER
MIN
MAX
F/2(1)
UNIT
MHz
ns
fclock(PIXEL_CLK)
tc(PIXEL_CLK)
Clock frequency, pixel clock
1
2
Cycle time, pixel clock
23.81
tw(PIXEL_CLK_H)
tw(PIXEL_CLK_L)
td(LCD_D_V)
Pulse duration, pixel clock high
10
10
0
ns
3
Pulse duration, pixel clock low
ns
4
Delay time, LCD_PCLK↑ to LCD_D[15:0] valid (write)
Delay time, LCD_PCLK↑ to LCD_D[15:0] invalid (write)
Delay time, LCD_PCLK↓ to LCD_AC_ENB_CS↑
Delay time, LCD_PCLK↓ to LCD_AC_ENB_CS↓
Delay time, LCD_PCLK↓ to LCD_VSYNC↑
Delay time, LCD_PCLK↓ to LCD_VSYNC↓
Delay time, LCD_PCLK↑ to LCD_HSYNC↑
Delay time, LCD_PCLK↑ to LCD_HSYNC↓
12
12
12
12
12
12
12
12
ns
5
td(LCD_D_IV)
0
ns
6
td(LCD_AC_ENB_CS_A)
td(LCD_AC_ENB_CS_I)
td(LCD_VSYNC_A)
td(LCD_VSYNC_I)
td(LCD_HSYNC_A)
td(LCD_HSYNC_I)
0
ns
7
0
ns
8
0
ns
9
0
ns
10
11
0
ns
0
ns
(1) F = frequency of LCD_PCLK in ns
Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1)
register:
•
•
•
•
Vertical front porch (VFP)
Vertical sync pulse width (VSW)
Vertical back porch (VBP)
Lines per panel (LPP)
Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register:
•
•
•
•
Horizontal front porch (HFP)
Horizontal sync pulse width (HSW)
Horizontal back porch (HBP)
Pixels per panel (PPL)
LCD_AC_ENB_CS timing is derived through the following parameter in the LCD (RASTER_TIMING_2)
register:
•
AC bias frequency (ACB)
The display format produced in raster mode is shown in Figure 6-54. An entire frame is delivered one line
at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line
delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is
denoted by the activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the
activation of I/O signal LCD_HSYNC.
182
Peripheral Information and Electrical Specifications
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