ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄꢆꢈ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢃ ꢆꢈ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢃꢆ ꢇ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS272F − JULY 2000 − REVISED JUNE 2004
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
USART1
(MSP430x14x and
MSP430x14x1 only)
Transmit buffer
U1TXBUF
U1RXBUF
U1BR1
U1BR0
U1MCTL
U1RCTL
U1TCTL
U1CTL
U0TXBUF
U0RXBUF
U0BR1
U0BR0
U0MCTL
U0RCTL
U0TCTL
U0CTL
CAPD
07Fh
07Eh
07Dh
07Ch
07Bh
07Ah
079h
078h
077h
076h
075h
074h
073h
072h
071h
070h
05Bh
05Ah
059h
058h
057h
056h
037h
036h
035h
034h
033h
032h
031h
030h
01Fh
01Eh
01Dh
01Ch
01Bh
01Ah
019h
018h
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Receive buffer
Baud rate
Baud rate
Modulation control
Receive control
Transmit control
USART control
USART0
Transmit buffer
Receive buffer
Baud rate
Baud rate
Modulation control
Receive control
Transmit control
USART control
Comparator_A
Basic Clock
Port P6
Comparator_A port disable
Comparator_A control2
Comparator_A control1
Basic clock system control2
Basic clock system control1
DCO clock frequency control
Port P6 selection
Port P6 direction
Port P6 output
CACTL2
CACTL1
BCSCTL2
BCSCTL1
DCOCTL
P6SEL
P6DIR
P6OUT
P6IN
Port P6 input
Port P5
Port P4
Port P3
Port P2
Port P5 selection
Port P5 direction
Port P5 output
P5SEL
P5DIR
P5OUT
P5IN
Port P5 input
Port P4 selection
Port P4 direction
Port P4 output
P4SEL
P4DIR
P4OUT
P4IN
Port P4 input
Port P3 selection
Port P3 direction
Port P3 output
P3SEL
P3DIR
P3OUT
P3IN
Port P3 input
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt-edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
Port P2 input
22
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