MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh
15, highest
Flash memory
NMI
Oscillator fault
Flash memory access violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
0FFFAh
0FFF8h
14
13
12
Timer1_A5 (see Note 4)
TA1CCR0 CCIFG (see Note 2)
Maskable
TA1CCR1 to TA1CCR4
CCIFGs and TA1CTL TAIFG
(see Notes 1 and 2)
Timer1_A5 (see Note 4)
Maskable
Comparator_A
Watchdog timer
CMPAIFG
WDTIFG
Maskable
Maskable
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
11
10
9
8
7
Timer_A3/Timer0_A3
TACCR0/TA0CCR0 CCIFG
(see Note 2)
Maskable
6
TACCR1/TA0CCR1,
TACCR2/TA0CCR2 CCIFGs
and TACLT/TA0CTL TAIFG
(see Notes 1 and 2)
Timer_A3/Timer0_A3
I/O port P1 (eight flags)
Maskable
Maskable
0FFEAh
0FFE8h
5
4
P1IFG.0 to P1IFG.7
(see Notes 1 and 2)
0FFE6h
0FFE4h
3
2
P2IFG.0 to P2IFG.7
(see Notes 1 and 2)
I/O port P2 (eight flags)
Maskable
Maskable
0FFE2h
0FFE0h
1
Basic Timer1
BTIFG
0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.
4. Implemented in MSP430x415 and MSP430x417 devices only
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