MSP430x13x, MSP430x14x
MIXED SIGNAL MICROCONTROLLER
SLAS272D – JULY 2000 – REVISED MARCH 2003
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh – 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE
Power-up
External Reset
Watchdog
Flash memory
NMI
Oscillator Fault
Flash memory access violation
Timer_B7 (see Note 5)
Timer_B7 (see Note 5)
Comparator_A
Watchdog timer
USART0 receive
USART0 transmit
ADC12
Timer_A3
Timer_A3
INTERRUPT FLAG
WDTIFG
KEYV
(see Note 1)
NMIIFG (see Notes 1 & 4)
OFIFG (see Notes 1 & 4)
ACCVIFG (see Notes 1 & 4)
TBCCR0 CCIFG (see Note 2)
TBCCR1 to 6 CCIFGs,
TBIFG (see Notes 1 & 2)
CAIFG
WDTIFG
URXIFG0
UTXIFG0
ADC12IFG (see Notes 1 & 2)
TACCR0 CCIFG (see Note 2)
TACCR1 CCIFG,
TACCR2 CCIFG,
TAIFG (see Notes 1 & 2)
P1IFG.0 (see Notes 1 & 2)
To
P1IFG.7 (see Notes 1 & 2)
URXIFG1
UTXIFG1
P2IFG.0 (see Notes 1 & 2)
To
P2IFG.7 (see Notes 1 & 2)
Maskable
SYSTEM INTERRUPT
Reset
WORD ADDRESS
0FFFEh
PRIORITY
15, highest
(Non)maskable
(Non)maskable
(Non)maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
0FFFCh
0FFFAh
0FFF8h
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
0FFEAh
14
13
12
11
10
9
8
7
6
5
I/O port P1 (eight flags)
USART1 receive
USART1 transmit
I/O port P2 (eight flags)
Maskable
Maskable
0FFE8h
0FFE6h
0FFE4h
0FFE2h
0FFE0h
4
3
2
1
0, lowest
NOTES: 1.
2.
3.
4.
Multiple source flags
Interrupt flags are located in the module.
Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable
it.
5. Timer_B7 in MSP430x14x family has 7 CCRs; Timer_B3 in MSP430x13x family has 3 CCRs. In Timer_B3 there are only interrupt
flags TBCCR0, 1, and 2 CCIFGs and the interrupt-enable bits TBCCTL0, 1, and 2 CCIEs.
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