MSP430FR573x
MSP430FR572x
SLAS639D –JULY 2011–REVISED AUGUST 2012
www.ti.com
MAX UNIT
10-Bit ADC, Power Supply and Input Range Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.0
0
TYP
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
AVCC
Analog supply voltage
Analog input voltage range
3.6
V
V
V(Ax)
All ADC10 pins
AVCC
140
Operating supply current into fADC10CLK = 5 MHz, ADC10ON = 1,
2 V
3 V
90
IADC10_A
AVCC terminal, reference
current not included
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC10DIV = 0
µA
100
160
Only one terminal Ax can be selected at one
time from the pad to the ADC10_A capacitor
array including wiring and pad
CI
RI
Input capacitance
2.2 V
6
8
pF
Input MUX ON resistance
AVCC ≥ 2 V, 0 V ≤ VAx ≤ AVCC
36
kΩ
10-Bit ADC, Timing Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
For specified performance of ADC10 linearity
parameters
2 V to
3.6 V
fADC10CLK
fADC10OSC
0.45
5
5.5 MHz
Internal ADC10 oscillator
(MODOSC)
2 V to
3.6 V
ADC10DIV = 0, fADC10CLK = fADC10OSC
4.5
4.5
5.5 MHz
REFON = 0, Internal oscillator,
12 ADC10CLK cycles, 10-bit mode,
fADC10OSC = 4.5 MHz to 5.5 MHz
2 V to
3.6 V
2.18
2.67
µs
tCONVERT
Conversion time
External fADC10CLK from ACLK, MCLK, or SMCLK,
ADC10SSEL ≠ 0
2 V to
3.6 V
(1)
The error in a conversion started after tADC10ON is
less than ±0.5 LSB,
Reference and input signal already settled
Turn on settling time of
the ADC
tADC10ON
100
ns
µs
RS = 1000 Ω, RI = 36000 Ω, CI = 3.5 pF,
Approximately eight Tau (τ) are required to get an
error of less than ±0.5 LSB
2 V
3 V
1.5
2.0
tSample
Sampling time
(1) 12 × ADC10DIV × 1/fADC10CLK
10-Bit ADC, Linearity Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.6 V
1.6 V < (VeREF+ – VREF–/VeREF–)min ≤ VAVCC
VCC
MIN
-1.4
-1.1
TYP
MAX UNIT
1.4
Integral
linearity error
2 V to
3.6 V
EI
LSB
1.1
Differential
linearity error
2 V to
3.6 V
ED
EO
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–
)
)
)
-1
-6.5
-1.2
-4
1
LSB
mV
2 V to
3.6 V
Offset error
6.5
Gain error, external
reference
2 V to
3.6 V
1.2 LSB
EG
Gain error, internal
4
2
%
(1)
reference
Total unadjusted
error, external
reference
2 V to
3.6 V
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–
)
-2
-4
LSB
ET
Total unadjusted
error, internal
4
%
(1)
reference
(1) Error is dominated by the internal reference.
64
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
