MSP430F663x
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
SHORT-FORM DESCRIPTION
Program Counter
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-to-
register operation execution time is one cycle of the
CPU clock.
R5
R6
R7
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
R8
R9
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
R10
R11
R12
Instruction Set
R13
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data. Table 4 shows examples of the three
types of instruction formats; Table 5 shows the
address modes.
R14
R15
Table 4. Instruction Word Formats
INSTRUCTION WORD FORMAT
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
EXAMPLE
ADD R4,R5
CALL R8
JNE
OPERATION
R4 + R5 → R5
PC → (TOS), R8 → PC
Jump-on-equal bit = 0
Table 5. Address Mode Descriptions
ADDRESS MODE
Register
S(1)
+
D(1)
+
SYNTAX
MOV Rs,Rd
EXAMPLE
OPERATION
MOV R10,R11
R10 → R11
Indexed
+
+
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV &MEM, &TCDAT
MOV @Rn,Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
M(R10) → M(Tab+R6)
Symbolic (PC relative)
Absolute
+
+
+
+
Indirect
+
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
M(R10) → R11
R10 + 2 → R10
Indirect auto-increment
Immediate
+
+
MOV @Rn+,Rm
MOV #X,TONI
#45 → M(TONI)
(1) S = source, D = destination
Copyright © 2010–2012, Texas Instruments Incorporated
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