ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄꢆꢈ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢃ ꢆꢈ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢃꢆ ꢇ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS272F − JULY 2000 − REVISED JUNE 2004
special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
7
6
5
4
3
2
1
0
Address
0h
UTXIE0
URXIE0
ACCVIE
NMIIE
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
WDTIE:
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE:
Oscillator-fault-interrupt enable
NMIIE:
Nonmaskable-interrupt enable
ACCVIE:
URXIE0:
UTXIE0:
Flash access violation interrupt enable
USART0: UART and SPI receive-interrupt enable
USART0: UART and SPI transmit-interrupt enable
7
6
5
4
3
2
1
0
Address
01h
UTXIE1
URXIE1
rw-0
rw-0
URXIE1:
UTXIE1:
USART1: UART and SPI receive-interrupt enable
USART1: UART and SPI transmit-interrupt enable
interrupt flag register 1 and 2
7
6
URXIFG0
rw-0
5
4
3
2
1
0
Address
02h
UTXIFG0
NMIIFG
OFIFG
WDTIFG
rw-1
rw-0
rw-1
rw-(0)
WDTIFG:
Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on V
power up or a reset condition at the RST/NMI pin in reset mode.
CC
OFIFG:
Flag set on oscillator fault
Set via RST/NMI pin
NMIIFG:
URXIFG0: USART0: UART and SPI receive flag
UTXIFG0: USART0: UART and SPI transmit flag
7
6
5
4
3
2
1
0
Address
03h
UTXIFG1
URXIFG1
rw-1
rw-0
URXIFG1: USART1: UART and SPI receive flag
UTXIFG1: USART1: UART and SPI transmit flag
14
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