SNVS764Q – JANUARY 2000 – REVISED DECEMBER 2017
7.4 Thermal Information: LP2950-N
LP2950-N
THERMAL METRIC
R
θJA
(2)
R
θJC(top)
R
θJB
ψ
JT
ψ
JB
R
θJC(bot)
(1)
(2)
(3)
(1)
LP (TO-92)
3 PINS
157.4
81.2
153.6
25.2
n/a
n/a
NDP (TO-252)
3 PINS
51.3
(3)
53.5
30.4
5.5
30
2.2
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-ambient thermal resistance, High-K
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
For more information about traditional and new thermal metrics, see the
application
report.
Thermal resistance value R
θJA
is based on the EIA/JEDEC High-K printed circuit board defined by
JESD51-7 - High Effective Thermal
Conductivity Test Board for Leaded Surface Mount Packages.
The PCB for the TO-252 (NDP) package R
θJA
includes twelve (12) thermal vias under the tab per EIA/JEDEC JESD51-5.
7.5 Thermal Information: LP2951-N
LP2951-N
THERMAL METRIC
(1)
P (PDIP)
8 PINS
R
θJA
R
θJB
ψ
JT
ψ
JB
R
θJC(bot)
(1)
(2)
(3)
(2)
D (SOIC)
8 PINS
117.7
63.7
57.9
15.9
57.5
n/a
DGK
(VSSOP)
8 PINS
171.0
62.3
91.4
8.9
90.1
n/a
NGT
(WSON)
8 PINS
43.3
(3)
35.0
23.3
0.5
20.5
9.1
UNIT
Junction-to-ambient thermal resistance, High K
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
56.3
45.7
33.5
22.9
33.3
n/a
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
R
θJC(top)
For more information about traditional and new thermal metrics, see the
application
report.
Thermal resistance value R
θJA
is based on the EIA/JEDEC High-K printed circuit board defined by
JESD51-7 - High Effective Thermal
Conductivity Test Board for Leaded Surface Mount Packages.
The PCB for the WSON (NGT) package R
θJA
includes six (6) thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5.
6
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